![]() ![]() In this way, the 2nd CLK signal ‘Q2’ will vary from ‘0’ to ‘1’. But, the ‘Q3’ output will vary from ‘0’ to ‘1’ once the 1st CLK signal arrives while the remaining o/ps are still ‘0’. In addition, the above-shown waveform will represent the 4 data o/p of the FFs.įirstly, all the FFs o/ps were ‘0’ which is very clearly given in the above representation of the waveform. ![]() So the waveform will be a constant high signal. In the above waveform, the 1st waveform is the CLK i/p signal whereas the 2nd waveform shows the data i/p to be stored as ‘1111’. The SISO shift register truth table is shown below.īy considering the above truth table, the SISO shift register waveform representation will be like the following. Therefore, finally, SISO shift register store 1111 bit & shows in the o/p. In addition, an MSB bit like high signal (1) is given as input, after that ‘1’ at ‘Q1’ will cause input ‘D0’ to be ‘1’, thus, this will make ‘Q0’ be ‘1’. So the overall o/p for the 3rd falling edge will get o/p as “1110”. This will give the output Q3, Q2 & Q1 as ‘1’ whereas ‘Q0’ will be ‘0’. When the third input bit like high signal (1) is applied at the ‘D3’ FF then earlier ‘Q2’ o/p will cause the ‘D1’ i/p to be ‘0’. ![]()
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